`timescale 1ns / 1ps

module tb_fc_top();

    reg         clk;
    reg         rst_n_fc;
    reg         start;
    wire        done_o;

    wire [31:0] fc1_output_data_monitor;
    wire          fc1_output_wren_monitor;

    wire [47:0] fc2_output_data_monitor;
    wire        fc2_output_wren_monitor;

    wire signed [63:0] fc3_output_data_monitor;
    wire        fc3_output_wren_monitor;
    fc_top u_fc_top(
        .clk(clk),
        .rst_n(rst_n_fc),
        .start(start),
        .done_o(done_o),
        .fc1_output_data_monitor(fc1_output_data_monitor),
        .fc1_output_wren_monitor(fc1_output_wren_monitor),
        .fc2_output_data_monitor(fc2_output_data_monitor),
        .fc2_output_wren_monitor(fc2_output_wren_monitor),
        .fc3_output_data_monitor(fc3_output_data_monitor),
        .fc3_output_wren_monitor(fc3_output_wren_monitor)
    );

    integer file_handle1, file_handle2, file_handle3;
    initial begin
        file_handle1 = $fopen("D:/Verilog/FullConnectionLayer/output1.txt", "w");
        file_handle2 = $fopen("D:/Verilog/FullConnectionLayer/output2.txt", "w");
        file_handle3 = $fopen("D:/Verilog/FullConnectionLayer/output3.txt", "w");
    end

    always @(negedge clk) begin    //在clk的下降沿切中fc_output_wren_monitor
        if (fc1_output_wren_monitor) begin
            $fwrite(file_handle1, "%d\n", fc1_output_data_monitor);
        end
    end

    always @(posedge clk) begin
        if (fc2_output_wren_monitor) begin
            $fwrite(file_handle2, "%d\n", fc2_output_data_monitor);
        end
    end

    always @(posedge clk) begin
        if (fc3_output_wren_monitor) begin
            $fwrite(file_handle3, "%d\n", fc3_output_data_monitor);
        end
    end

    initial begin
        forever #5 clk = ~clk;
    end

    initial begin
        clk = 0;
        rst_n_fc = 0;
        start = 0;
        #20 rst_n_fc = 1;
        #10 start = 1;
    end

    always @(posedge clk) begin
        if(done_o) begin
            start = 0;
            $finish;
        end      
    end

endmodule